Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device having a One-Side-Contact (OSC) structure and a method for fabricating the same.
When buried bit lines (BBL) are used in cells of a vertical gate (VG), two cells are adjacent to one buried bit line. In order for only one cell to be driven by the one buried bit line, a one-side contact is formed in the active region of one cell so that only that cell is driven and the adjacent cell is insulated. Herein, a one-side contact refers to a portion along one sidewall of an active region that permits electrical contact between the active region and its corresponding bit line.
The height of the buried bit lines is often short, and therefore, it can be difficult to form the one-side contact in a portion of a sidewall of an active region so that the active region and a buried bit line are coupled.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
Referring to FIG. 1A, a hard mask pattern 12 is formed over a semiconductor substrate 11.
Subsequently, a plurality of trenches 13 are formed by using the hard mask pattern 12 as an etch barrier and etching the semiconductor substrate 11 to a certain depth. The plurality of the trenches 13 define a plurality of active regions 101 that are separated from each other by the trenches 13.
Subsequently, a first insulation layer 14 and a second insulation layer 15 are sequentially formed. Then, a polysilicon layer 16 gap-filling the plurality of the trenches 13 is formed.
Referring to FIG. 1B, the polysilicon layer 16 is planarized through a Chemical Mechanical Polishing (CMP) method until the surface of the hard mask pattern 12 is exposed. Then, an etch-back process is performed to recess the planarized polysilicon layer 16 using the hard mask pattern 12 as an etch barrier. As a result, recessed polysilicon layers 16A and 16B are formed. As shown in FIG. 1B, the recessed polysilicon layers 16A and 16B may have different heights.
Referring to FIG. 1C, the recessed polysilicon layers 16A and 16B are etched using an OSC mask (not shown). As a result, recesses R1 and R2 are created to form openings used to subsequently form one-side contacts.
The conventional technology, however, cannot exactly control the height of the recessed polysilicon layers 16A and 16B resulting from the etch-back process due to the presence of a seam or void 17 which is caused when the polysilicon layer 16 is gap-filled. Also, since horns 18 may be formed in the plurality of the trenches 13 of approximately 3000 Å or higher, it is difficult to form the one-side contact at a desired position. Moreover, the depth of the recesses R1 and R2 may not be uniform due to the presence of the seam or void 17.